FM25040A
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
128 x 32
FRAM Array
Instruction Register
Address Register
Counter
SI
9
8
Data I/O Register
2
Nonvolatile Status
Register
SO
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
Description
Chip Select. This active-low input activates the device. When high, the device enters low-
power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the
device internally activates the SCK signal. A falling edge on /CS must occur prior to every
op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the
rising edge and outputs occur on the falling edge. Since the device is static, the clock
frequency may be any value between 0 and 20 MHz and may be interrupted at any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for
another task. When /HOLD is low, the current operation is suspended. The device ignores
any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low.
Write Protect: This active-low pin prevents all write operations, including those to the
status register. If high, write access is determined by the other write protection features, as
controlled through the status register. A complete explanation of write protection is
provided on page 6.
Serial Input: All input data is driven to this pin. The pin is sampled on the rising edge of
SCK and is ignored at other times. It should always be driven to a valid logic level to meet
I
DD
specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: SO is the data output pin. It is driven actively during a read and remains tri-
state at all other times including when /HOLD is low. Data transitions are driven on the
falling edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part communicates in
half-duplex fashion.
Supply Voltage: 5V
Ground
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 3.0
May 2006
Page 2 of
13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
