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FM24V01-G 参数 Datasheet PDF下载

FM24V01-G图片预览
型号: FM24V01-G
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, 16KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8]
分类和应用: PC静态存储器光电二极管内存集成电路
文件页数/大小: 14 页 / 372 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM24V01 - 128Kb I2C FRAM  
Electrical Specifications  
Absolute Maximum Ratings  
Symbol  
VDD  
VIN  
Description  
Power Supply Voltage with respect to VSS  
Voltage on any pin with respect to VSS  
Ratings  
-1.0V to +4.5V  
-1.0V to +4.5V  
and VIN < VDD+1.0V *  
TSTG  
TLEAD  
VESD  
Storage Temperature  
Lead Temperature (Soldering, 10 seconds)  
Electrostatic Discharge Voltage  
-55C to +125C  
260C  
- Human Body Model (AEC-Q100-002 Rev. E)  
- Charged Device Model (AEC-Q100-011 Rev. B)  
- Machine Model (AEC-Q100-003 Rev. E)  
Package Moisture Sensitivity Level  
3.5kV  
1.25kV  
200V  
MSL-1  
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating  
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this  
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = -40C to + 85C, VDD =2.0V to 3.6V unless otherwise specified)  
Symbol Parameter  
Min  
Typ  
Max  
Units  
Notes  
VDD  
IDD  
Main Power Supply  
2.0  
3.3  
3.6  
V
VDD Supply Current  
@ SCL = 100 kHz  
@ SCL = 1 MHz  
@ SCL = 3.4 MHz  
1
90  
200  
500  
175  
400  
1000  
A  
A  
A  
A  
A  
A  
A  
V
ISB  
IZZ  
ILI  
ILO  
VIL  
VIH  
VOL1  
VOL2  
RIN  
Standby Current  
Sleep Mode Current  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
80  
4
150  
8
±1  
2
2
3
3
±1  
-0.3  
0.7 VDD  
0.3 VDD  
VDD + 0.3  
0.4  
Input High Voltage  
V
V
V
Output Low Voltage (IOL = 2 mA, VDD 2.7V)  
Output Low Voltage (IOL = 150 A)  
Address Input Resistance (WP, A2-A0)  
For VIN = VIL (max)  
0.2  
50  
1
4
K  
M  
For VIN = VIH (min)  
Notes  
1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.  
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.  
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.  
4. The input pull-down circuit is stronger (50K) when the input voltage is below VIL and weak (1M) when the input voltage  
is above VIH.  
Rev. 3.0  
Jan. 2012  
Page 10 of 14