FM24CL64
Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
tHIGH
tR
tSP
tF
tSP
tLOW
`
SCL
SDA
1/fSCL
tSU:SDA
tHD:DAT
tSU:DAT
tBUF
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Data Retention (VDD = 2.7V to 3.65V, 85°C)
Parameter
Min
Units
Notes
Data Retention
45
Years
Rev. 3.1
Mar. 2005
Page 10 of 13
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