FM24CL64B
Equivalent AC Load Circuit
3.6V
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
1100
Output
Diagram Notes
All start and stop timing parameters apply to both read and write cycles.
Clock specifications are identical for read and write cycles. Write timing
parameters apply to slave address, word address, and write data bits.
Functional relationships are illustrated in the relevant datasheet sections.
These diagrams illustrate the timing parameters only.
100 pF
Read Bus Timing
tHIGH
tR
tSP
tF
tSP
tLOW
`
SCL
1/fSCL
tSU:SDA
tHD:DAT
tSU:DAT
tBUF
SDA
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Data Retention
Symbol
TDR
Parameter
@ +85ºC
@ +80ºC
@ +75ºC
Min
Max
Units
Years
Years
Years
Notes
10
19
38
-
-
-
Rev. 3.0
Jan. 2012
Page 10 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
