FM24CL04
Overview
The FM24CL04 is a serial FRAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard two-wire
interface. Functional operation of the FRAM is
similar to serial EEPROMs. The major difference
between the FM24CL04 and a serial EEPROM with
the same pinout relates to its superior write
performance.
Two-wire Interface
The FM24CL04 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24CL04 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL04 is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. Figure 3
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications.
Memory Architecture
When accessing the FM24CL04, the user addresses
512 locations each with 8 data bits. These data bits
are shifted serially. The 512 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other devices), a page address,
and a word address. The word address consists of 8-
bits that specify one of 256 addresses. The page
address is 1-bit and so there are 2 pages each of 256
locations. The complete address of 9-bits specifies
each byte address uniquely.
Most functions of the FM24CL04 either are
controlled by the two-wire interface or are handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
Users can expect several obvious system benefits
from the FM24CL04 due to its fast write cycle and
high endurance as compared with EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since it is completed quickly. By contrast
an EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM24CL04 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that V
DD
is within data sheet tolerances to prevent
incorrect operation.
D
E
D S
N N
E G
M SI
4B
M E
L0
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
VDD
Microcontroller
Rmin = 1.1 KΩ
Rmax = tR/Cbus
SDA
SCL
SDA
SCL
FM24CL04
FM24CL64
A1 A2
A0 A1 A2
Figure 2. Typical System Configuration
Rev. 3.2
Feb. 2011
Page 3 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
