FM22L16
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
tZZEN
tZZEX
Notes
Parameter
Min
450
Max
Units
Notes
Power-Up to First Access Time (after VDD min)
Power-Down to Last Access Time (prior to VTP)
VDD Rise Time
-
0
-
-
0
-
µs
µs
µs/V
µs/V
µs
50
100
-
1,2
1,2
VDD Fall Time
Sleep Mode Enter Time (/ZZ low to /CE don’t care)
Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)
450
µs
1
2
Slope measured at any point on VDD waveform.
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
0 to 3V
3 ns
1.5V
30pF
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 1.0
Mar. 2007
Page 10 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
