FM21LD16 - 128Kx16 FRAM
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
450
0
Max
Units
µs
Notes
tPU
Power-Up (after VDD min. is reached) to First Access Time
Last Write (/WE high) to Power Down Time
VDD Rise Time
-
-
-
-
tPD
µs
tVR
50
100
1,2
1,2
µs/V
µs/V
tVF
Notes
VDD Fall Time
1
Slope measured at any point on VDD waveform.
2
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
0 to 3V
Input and Output Timing Levels
Output Load Capacitance
1.5V
30pF
Input Rise and Fall Times 3 ns
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 1.1
Apr. 2011
Page 11 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
