FM21LD16 - 128Kx16 FRAM
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
Parameter
Min
450
0
50
100
Max
Units
µs
µs
µs/V
µs/V
Notes
Power-Up (after VDD min. is reached) to First Access Time
Last Write (/WE high) to Power Down Time
VDD Rise Time
-
-
-
-
1,2
1,2
VDD Fall Time
Notes
1
2
Slope measured at any point on VDD waveform.
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times 3 ns
0 to 3V
Input and Output Timing Levels
Output Load Capacitance
1.5V
30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 1.0
Dec. 2009
Page 10 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
