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DM2M36SJ6-15I 参数 Datasheet PDF下载

DM2M36SJ6-15I图片预览
型号: DM2M36SJ6-15I
PDF下载: 下载PDF文件 查看货源
内容描述: [Cache DRAM Module, 2MX36, 35ns, MOS, SIMM-72]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 20 页 / 198 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号DM2M36SJ6-15I的Datasheet PDF文件第6页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第7页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第8页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第9页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第11页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第12页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第13页浏览型号DM2M36SJ6-15I的Datasheet PDF文件第14页  
Switching Characteristics  
CC  
V = 5V ± 5% (+5 Volt Option), Vcc = 3.3V ± 0.3V (+3.3 Volt Option), C = 50pf, T = 0 to 70°C (Commercial), -40 to 85°C (Industrial)  
L
A
-12  
-15  
Symbol  
Description  
Units  
Min  
Max  
Min  
Max  
(1)  
t
Column Address Access Time  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AC  
t
t
Column Address Valid to /CAL Inactive (Write Cycle)  
Column Address  
12  
12  
5
15  
15  
5
ACH  
ACI  
t
t
t
t
t
t
t
t
t
Column Address Change to Output Data Invalid  
AQX  
ASC  
ASR  
C
Column Address Setup Time  
5
5
5
5
Row Address Setup Time  
55  
65  
25  
6
Row Enable Cycle Time  
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only  
Column Address Latch Active Time  
ns  
ns  
ns  
ns  
ns  
20  
5
C1  
CAE  
CAH  
CH  
Column Address Hold Time  
0
0
5
5
Column Address Latch High Time (Latch Transparent)  
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)  
-2  
-2  
CHR  
t
t
0
0
Column Address Latch High to Write Enable Low (Multiple Writes)  
Column Address Latch High to Data Valid  
ns  
ns  
CHW  
CLV  
7
7
t
Column Address Latch Low to Data Invalid  
0
5
ns  
CQH  
t
t
t
t
t
t
t
t
Column Address Latch High to Data Invalid  
Column Address Latch Setup Time to Row Enable  
/WE Low to /CAL Inactive  
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CQV  
CRP  
CWL  
DH  
5
5
0
1
5
5
5
5
0
Data Input Hold Time  
1.5  
Mask Hold Time From Row Enable (Write-Per-Bit)  
Mask Setup Time to Row Enable (Write-Per-Bit)  
Data Input Setup Time  
DMH  
DMS  
DS  
5
5
(1)  
GQV  
Output Enable Access Time  
5
5
5
5
5
5
(2,3)  
GQX  
t
t
t
t
t
t
t
t
t
Output Enable to Output Drive Time  
0
0
0
0
ns  
ns  
(4,5)  
GQZ  
Output Turn-Off Delay From Output Disabled (/G)  
/F and W/R Mode Select Hold Time  
0
0
ns  
ns  
ns  
ns  
ns  
MH  
/F and W/R Mode Select Setup Time  
5
5
MSU  
NRH  
NRS  
PC  
/CAL, /G, W/R, and /WE Hold Time For /RE-Only Refresh  
/CAL, /G, W/R, and /WE Setup Time For /RE-Only Refresh  
Column Address Latch Cycle Time  
0
0
5
5
12  
15  
(1)  
RAC  
Row Enable Access Time, On a Cache Miss  
30  
15  
35  
17  
ns  
ns  
(1)  
Row Enable Access Time, On a Cache Hit (Limit Becomes t  
Row Enable Access Time for a Cache Write Hit  
Row Address Hold Time  
)
RAC1  
AC  
(1,6)  
t
t
t
30  
35  
ns  
ns  
ns  
RAC2  
RAH  
RE  
1
1.5  
35  
Row Enable Active Time  
100000  
30  
100000  
2-104