RA8835
Preliminary Version 1.2
Dot Matrix LCD Controller
Write Control or Read/Write Control.
When the 8080 family interface is selected, this signal acts as the active-LOW
write strobe. The bus data is latched on the rising edge of this signal.
When the 6800 family interface is selected, this signal acts as the read/write
control signal. Data is read from the RA8835 series if this signal is HIGH, and
written to the RA8835 series if it is LOW.
Chip Select.
This active-LOW input enables the RA8835 series. It is usually connected to the
output of an address decoder device that maps the RA8835 series into the
memory space of the controlling microprocessor.
Command/Data Select.
8080 Family Interface:
WR
or
R/
W
CS
A0
0
1
0
1
RD
0
0
1
1
WR
1
1
0
0
A0
Function
Status flag read
Display data and cursor address
read
Display data and parameter write
Command write
6800 Family Interface:
A0
0
1
0
1
R/
W
1
1
0
0
E
1
1
1
1
Function
Status flag read
Display data and cursor address
read
Display data and parameter write
Command write
RES
Hardware Reset.
This active-LOW input performs a hardware reset on the RA8835 series. It is a
Schmitt-trigger input for enhanced noise immunity; however, care should be
taken to ensure that it is not triggered if the supply voltage is lowered.
5.1.2 Display Memory Control
The RA8835 series can directly access static RAM and PROM. The designer may use a mixture of
these two types of memory to achieve an optimum trade-off between low cost and low power
consumption.
Pin Name
Function
16-bit Display Memory Address.
When accessing character generator RAM or ROM, VA0 to VA3, reflect the
lower 4 bits of the RA8835 row counter.
Display Memory Data Bus.
8-bit tri-state display memory data bus. These pins are enabled when
VRD
or
VWR
is LOW.
Display Memory Write Control.
Active-LOW display memory write control output.
Display Memory Read Control.
Active-LOW display memory read control output.
VA0 to VA15
VD0 to VD7
VWR
VRD
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