RA8835A
Version 1.0
Dot Matrix LCD Controller
10.3-4 Display Memory Write Timing
tC
EXT￠O
VA0 to VA15
tW
tCE
VCE
tASC
tCA
tAHC
tWSC
tAS
tWHC
tAH2
tDH2
VR/W
tDSC
tDHC
VD0 to VD7
Ta = –20 to 75℃
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal
Symbol
Parameter
Unit Condition
Min.
Max.
Min.
Max.
EXT Φ0
tC
Clock period
55.5
—
62.5
—
ns
ns
VCE HIGH-level
pulse width
tW
tC – 50
—
tC – 50
—
VCE
VCE LOW-level
pulse width
tCE
2tC – 30
3tC
—
—
2tC – 30
3tC
—
—
ns
ns
tCYW
Write cycle time
Address hold time
from falling edge of
tAHC
tASC
tCA
2tC – 30
—
—
—
—
—
2tC – 40
—
—
—
—
—
ns
ns
ns
VCE
Address setup time to
tC – 70
tC – 110
falling edge of VCE
Address hold time
from rising edge of
VA0 to
VA15
0
0
0
0
VCE
Address setup time to
CL = 100
pF
tAS
ns
ns
falling edge of VWR
Address hold time
from rising edge of
tAH2
10
10
VWR
Write setup time to
tWSC
tWHC
tC – 80
—
—
tC – 115
2tC – 20
—
—
ns
ns
falling edge of VCE
Write hold time from
VWR
2tC – 20
falling edge of VCE
Data input setup time
to falling edge of
tDSC
tC – 85
—
tC – 125
—
ns
VCE
Data input hold time
from falling edge of
VD0 to
VD7
tDHC
2tC – 30
5
—
2tC – 30
5
—
ns
ns
VCE
Data hold time from
tDH2
50
50
rising edge of VWR
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain
the write data until the data read from the memory is placed on the bus.
RAiO TECHNOLOGY INC.
www.raio.com.tw
84/88
RAIO [ RAIO TECHNOLOGY INC. ]
