RA8835A
Version 1.0
Dot Matrix LCD Controller
4. Package
XG
SEL1
SEL2
WR
RD
NC
NC
RES
VRD
VCE
VWR
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VD4
VD5
VD6
VD7
YSCL
YD
YDIS
WF
LP
GND
XSCL
SECL
XD0
XD1
XD2
45
46
31
30
XD
CS
A0
VDD
D0
D1
D2
D3
D4
D5
D6
50
45
40
35
RAiO
60
1
Index
TM
30
VA8
VA9
VA10
VA11
VA12
VA13
NC
VA14
VA15
VD0
VD1
VD2
RA8835AP3N
07xx
Date Code(Year 2007)
29
5
6
25
20
10
15
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
RAiO
TM
RA8835AP4N
07xx
Index
60
1
Date Code(Year 2007)
16
15
XD3
D7
D6
D5
D4
D3
D2
D1
D0
VDD
A0
CS
XD
XG
SEL1
D7
XD3
XD2
XD1
XD0
XECL
XSCL
GND
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3
Figure 4-1: RA8835AP3N(QFP-60 Pin)
Figure 4-2: RA8835AP4N (TQFP-60 Pin)
5. Pin Descriptions
5-1 Pin Functions
5-1-1 MCU Interface
Pin
Name
D0 to D7
Function
MCU Data Bus.
Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus.
MCU Interface Select.
The RA8835A series supports both 8080 family processors (such as the 8085 and
Z80®) and 6800 family processors (such as the 6802 and 6809).
SEL1
0
1
SEL2*
0
0
Interface
8080 family
6800 family
A0
A0
A0
RD
RD
WR
WR
VS5
VA4
VA3
VA2
VA1
VA0
VWR
VCE
VRD
RES
NC
NC
RD
WR
SEL2
SEL1,
SEL2
CS
CS
E
R/
W
CS
SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on
SEL1, decouple it to ground using a capacitor placed as close to the pin as possible.
RD
or
E
Read Control or Enable.
When the 8080 family interface is selected, this signal acts as the active-LOW read
strobe. The RA8835A series output buffers are enabled when this signal is active.
When the 6800 family interface is selected, this signal acts as the active-HIGH
enable clock.
Data is read from or written to the RA8835A series when this clock goes HIGH.
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