RA8835A
Version 1.0
Dot Matrix LCD Controller
7-16 Setting Character Generator Address
The CG RAM addresses in the VRAM address space are not mapped directly from the address in the
SAG register. The data to be displayed is at a CG RAM address calculated from SAG + character
code + ROW select address. This mapping is shown in Table-22A and –22B.
Table-22A: Character Fonts, Number of Lines ≤ 8 (M2 = 0, M1 = 0)
SAG
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code
+ROW select
address
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
R1
R0
CG RAM address VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Table-22B: Character Fonts, 9 ≤ Number of Lines ≤ 16 (M2 = 1, M1 = 0)
SAG
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code
+ROW select
address
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R3 R2 R1 R0
CG RAM address VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Figure 7-28: Row Select Address
Note: Lines = 1: lines in the character bitmap ≤ 8
Lines = 2: lines in the character bitmap ≤ 9
7-16-1 M1 = 1
The RA8835A series automatically converts all bits set in bit 6 of character code for CG RAM 2 to
zero. Because of this, the CG RAM data areas become contiguous in display memory.
When writing data to CG RAM:
• Calculate the address as for M1 = 0.
• Change bit 6 of the character code from “1” to “0”.
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