RA8816
Preliminary Version 1.6
144x65 Character/Graphic LCD Driver
[11h] Driver Control Register1 (DRCR_A)
RW
0
DB7
DB6
DB5
DB4
DB3
IDIR
DB2
--
DB1
DB0
BOFF
EN_R
EN_G
ROFF
CDIR
SDIR
BOFF: Booster control. 1 Î Internal Booster enable. 0Î Internal Booster disabled and used external
voltage.
EN_R: Reference voltage control. 1 Î Internal reference voltage enable for Regulator. 0 Î Disable the
internal reference voltage. The Regulator use external reference voltage.
EN_G: V0 control. 1 Î The V0 is generated by internal Regulator. 0 Î Use external power for V0, and the
EN_R and BOFF have to clear “0”(Off) to reduce power consumption.
ROFF: Voltage Follower control. 1 Î Internal Voltage Follower enable for LCD Bias voltage. 0 Î Disable
internal Voltage Follower, and use external voltage to generate LCD Bias voltage. If use external
Voltage Follower, then EN_G, EN_R and BOFF have to clear “0”(Off) to reduce power
consumption.
IDIR : Icon sequence select. 0 Î Icon sequence is fixed. 1Î Icon sequence follow the setting of
CDIR/SDIR.
CDIR: Common sequency select. 0 Î Pins COM0~63 are mapping to Common 0~63. 1Î Pins COM0~63
are mapping to Common 63~0.
SDIR: Segment sequency select. 0 Î Pins SEG0~143 are mapping to Segment 0~143. 1Î Pins
SEG0~143 are mapping to Segment 143~0.
[12h] Driver Control Register (DRCR_B)
RW
0
DB7
DB6
DB5
RR2
DB4
RR1
DB3
RR0
DB2
IRS
DB1
HD1
DB0
HD0
CK_BS1 CK_BS0
CK_BS[1..0]: Select the clock of Booster. Assume the RC oscillator clock is 100KHz.
Table 5-15
CK_BS1 CK_BS0
Clock of Booster
0
0
1
1
0
1
0
1
SYS_CLK/2 Æ 50KHz
SYS_CLK/4 Æ 25KHz
SYS_CLK/6 Æ 16.7KHz
SYS_CLK/8 Æ 12.5KHz
RR[2..0]: Setup the Resistor Ratio of Regulator. The ratio is VREF : V0. Please refer to Section 6-4-2.
Table 5-16
RR2 RR1 RR0
Resistor Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X3
X3.5
X4
X4.5
X5
X5.5
X6
X6.4
Note: The VREF is 2.1V.
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