RA8806
Preliminary Version 1.0
Two Layers Character/Graphic LCD Controller
6-1-3 Memory Write/Read
When users want to write data to memory – DDRAM or CGRAM, then a special Command cycle
has to execute first, the register have to assign to “B0h” on Data Bus. Then the following Data Write
cycle will write data into memory. If users want to read data from memory, then the register has to
assign to “B1h” on Data Bus in Command Write cycle. Please see the following Figure 6-6 (1) and
(2).
RS
ZCS1
ZWR
ZRD
DATA[7:0]
B0h
DATA1
DATA2
DATAn
(1) Memory Write (Write Data to DDRAM)
RS
ZCS1
ZWR
ZRD
DATA[7:0]
B1h
DATA1
DATA2
DATAn
(2) Memory Read (Read Data from DDRAM)
Figure 6-6 : Memory Write/Read Cycle
6-1-4 Status Read
RA8806 provides a dedicate Status Read cycle to help users know the status of RA8806. Please
refer to following Figure 6-7 and the beginning of Section 5-2 “Register Description”.
RS
ZCS1
ZWR
ZRD
DATA[7:0]
Status DATA
Status Register Read
Figure 6-7 : Status Read Cycle
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