RA8806
Preliminary Version 1.0
Two Layers Character/Graphic LCD Controller
5-2 Register Description
STATUS Register (RS = 1, ZWR = 1)
Bit
Description
Access
Memory Write Busy Flag
0 : Not busy.
7
R
1 : Busy, when font write or memory clear cycle is running, the busy
flag = 1.
SCAN_BUSY
0 : Not busy.
6
5
R
R
1 : When driver scan logic is not idle(i.e. XCK is active), SCAN_BUSY
= 1.
SLEEP
0 : Normal mode.
1 : Sleep mode.
NA
4-3
2
R
R
Wakeup Status bit
(The same with REG[0Fh] Bit-2.)
KS Status bit
(The same with REG[0Fh] Bit-1.)
TP Status bit
1
0
R
R
(The same with REG[0Fh] Bit-0.)
REG [00h] Whole Chip LCD Controller Register (WLCR)
Bit
Description
Default
Access
Power Mode
0 : Normal Mode. All of the functions of RA8806 are available in this
mode.
1 : Sleep Mode. When RA8806 is in Sleep mode, all of functions enter
off mode, except the wake-up trigger block. If wake-up event
occurred, RA8806 would wake-up and return to Normal mode.
7
0
R/W
Linear Decode mode
This bit is used to define the Font ROM address mapping rule. The
standard product is set to 0. And 1 for special application that when
user a want to create a new Mask Code.
6
0
R/W
0 : BIG5/GB ROM mapping rule.
1 : User-defined ROM mapping rule.
Software Reset
0 : Normal Operation.
1 : Reset all registers except the contents of Display Data RAM (Only
work at Normal mode). When this bit set to “1”, the next MPU
cycle for RA8806 have to wait 3 clocks at least.
5
4
3
0
0
0
R/W
R
Reserved
Text Mode Selection
0 : Graphical Mode. The written data will be treated as a bit-map
pattern.
R/W
1 : Text Mode. The written data will be treated as an ASCII, BIG5 or
GB code.
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