2.17 Wiring
Table 2.2 - Pin Listing
Applies to all devices
Pin
1
2
Function
I/O
I/O
O
Comments
If Unused, Connect To..
Leave open
MOSI
MISO
SCK
SPI data input
SPI data output
SPI clock input
Reset low;
Leave open
Leave open
3
I/O
4
/RST
I
Vdd
has internal 30K ~ 60K pull-up
Power, +5V
5
6
7
8
9
Vdd
Vss
XT2
XT1
Rx
P
P
O
I
-
-
Supply ground
Leave open
16 MHz 3-terminal resonator
UART receive data input
-
I
Vdd
UART transmit data;
10
11
12
Tx
WS
O
I
Leave open
has internal 20K ~ 50K pull-up
Wake-up from sleep input and/or sync input
Vdd
-
Sample output. Also - When forced high before
SMP
I/O
reset, induces ‘factory defaults’ into all setups.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Y3A
Y2A
Y1A
Y0A
Vdd
Vss
X0
X1
X2
X3
X4
X5
X6
X7
Vdd
Vss
Vdd
Y0B
Y1B
Y2B
Y3B
I
I
I
Y line connection
Y line connection
Y line connection
Y line connection
Power, +5V
Leave open
Leave open
Leave open
Leave open
-
I
P
P
O
O
O
O
O
O
O
O
P
P
P
I
Supply ground
-
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
Power, +5V
Supply ground
Power, +5V
Y line connection
Y line connection
Y line connection
Y line connection
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
-
-
-
Leave open
Leave open
Leave open
Leave open
I
I
I
34
Y4A
I
Y line connection
Leave open
35
Y4B
I
Y line connection
36
37
38
39
40
Y5A
Y5B
Vdd
Vss
I
I
Y line connection
Leave open
Y line connection
P
P
O
Power, +5V
-
-
Supply ground
Status output / LED indicator drive
LED
Leave open
1= Comms ready;
41
DRDY
O
-
has internal 20K ~ 50K pull-up
42
43
Vref
S_Sync
I
O
0.05V nominal +/-10% via external divider
Scope Sync: Synchronization test signal
-
Leave open
SPI slave select;
44
/SS
I
Leave open
has internal 20K ~ 50K pull-up
lQ
9
QT60486-AS R8.01/0105
QUANTUM [ QUANTUM RESEARCH GROUP ]
