2.3 Response Time
The response time of the device depends on the scan rate of
the keys (Section 5.13), the number of keys enabled (Section
5.4), the detect integrator settings (Section 5.4), and the serial
polling rate by the host microcontroller (or the use of the LED
pin as an interrupt to the host; Sections 5.16, and Table 5.2 on
page 25). An example timing:
Keys enabled (KE) = 20
Burst spacing (BS) = 1ms
NDIL = 3
FDIL = 5
Host polling rate (PR) = 10ms
The worst case response time is computed as:
((KE + FDIL) x NDIL x BS) + PR = Worst case response
((20 + 5) x 3 x 1ms) + 10ms = 85ms
The use of the LED pin to trigger host sampling can reduce this
to ~75ms by saving the majority of the host polling time; see
Section 5.16.
increasing BL to a high count and watching what the waveform
does as it descends towards and below -0.25V. The waveform
will appear deceptively straight, but it will start to flatten even
before the -0.25V level is reached.
A correct waveform is shown in Figure 2-3. Note that the
bottom edge of the bottom trace is substantially straight
(ignoring the downward spikes).
Unlike other QT circuits, the Cs capacitor values on QT60xx6
devices have no effect on conversion gain. However they do
affect conversion time.
Unused Y lines should be left open.
2.6 Sample Resistors
There are 6 sample resistors (Rs) used to perform single-slope
ADC conversion of the acquired charge on each Cs capacitor.
These resistors directly control acquisition gain: larger values of
Rs will proportionately increase signal gain. Values of Rs can
range from 220K✡ to 1M✡. 220K✡ is a reasonable value for
most purposes.
Larger values for Rs will also increase conversion time and may
reduce the fastest possible key sampling rate, which can impact
response time especially with larger numbers of enabled keys.
Unused Y lines do not require an Rs resistor.
2.4 Oscillator
The oscillator can use either a quartz crystal or a ceramic
resonator. In either case, the XT1 and XT2 must both be loaded
with 22pF capacitors to ground. 3-terminal resonators having
onboard ceramic capacitors are commonly available and are
recommended. An external TTL-compatible frequency source
can also be connected to XT1 in which case, XT2 should be left
unconnected.
The frequency of oscillation should be 16MHz +/-1% for
accurate UART transmission timing.
Figure 2-1 VCs - Non-Linear During Burst
(Burst too long, or Cs too small, or X-Y capacitance too large)
2.5 Sample Capacitors; Saturation Effects
The charge sampler capacitors on the Y pins should be the
values shown. They should be X7R or NP0 ceramics or PPS
film. The value of these capacitors is not critical but 4.7nF is
recommended for most cases.
Cs voltage saturation is shown in Figure 2-1. This nonlinearity
is caused by excessively negative voltage on Cs inducing
conduction in the pin protection diodes. This badly saturated
signal destroys key gain and introduces a strong thermal
coefficient which can cause 'phantom' detection. The cause of
this is usually from the burst length being too long, the Cs value
being too small, or the X-Y coupling being too large. Solutions
include loosening up the interdigitation of key structures,
separating X and Y lines on the PCB more, increasing Cs, and
decreasing the burst length.
Increasing Cs will make the part slower; decreasing burst
length will make it less sensitive. A better PCB layout and a
looser key structure (up to a point) have no negative effects.
Cs voltages should be observed on an oscilloscope with the
matrix layer bonded to the panel material; if the Rs side of any
Cs ramps more negative than -0.25 volts during any burst (not
counting overshoot spikes which are probe artifacts), there is a
potential saturation problem.
Figure 2-2 shows a defective waveform similar to that of 2-1,
but in this case the distortion is caused by excessive stray
capacitance coupling from the Y line to AC ground, for example
from running too near and too far alongside a ground trace,
ground plane, or other traces. The excess coupling causes the
charge-transfer effect to dissipate a significant portion of the
received charge from a key into the stray capacitance. This
phenomenon is more subtle; it can be best detected by
Figure 2-2 VCs - Poor Gain, Non-Linear During Burst
(Excess capacitance from Y line to Gnd)
Figure 2-3 Vcs - Correct
lQ
4
QT60486-AS R8.01/0105
QUANTUM [ QUANTUM RESEARCH GROUP ]
