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QT60485-S 参数 Datasheet PDF下载

QT60485-S图片预览
型号: QT60485-S
PDF下载: 下载PDF文件 查看货源
内容描述: 32 , 48 , 64 KEY QMatrix KEYPANEL传感器IC [32, 48, 64 KEY QMatrix KEYPANEL SENSOR ICS]
分类和应用: 传感器
文件页数/大小: 42 页 / 810 K
品牌: QUANTUM [ QUANTUM RESEARCH GROUP ]
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© Quantum Research Group Ltd.  
obtained; see Section 5.7. Conversely longer spacings permit TLC2272 type opamp is a good example of the type of device  
which should be employed.  
higher burst lengths but slow down response time.  
Spacings from 250µs to 2ms are available.  
Figure 3-1 Circuit: The first opamp is a charge integrator  
whose output ranges between 0V to -2.5V. A JFET is used as  
a reset switch for the integration capacitor C14. Since most  
opamps are not fast enough to integrate the nanosecond  
duration transient charge pulses coming from the Y lines and  
the switched Cz capacitors, a large, non-critical capacitor C11  
is used to temporarily store transient charge until the opamp  
can assimilate it over the following microseconds.  
3.9 PLD Circuit and Charge Sampler  
The PLD should be a CMOS 22V10 type having no internal  
pullup or bus-keeper resistors in order to limit leakage  
current. ICTs PEEL22CV10AZ is a good example device,  
and code for this part can be found in Section 6.  
The PLD performs two functions: Y line clamping and transfer  
switch gating.  
The second stage opamp must invert the first opamp output  
in order to provide a positive-going signal to Ain of the  
QT60xx5. This stage is also used to facilitate the introduction  
of offset from the R2R network (Section 3.12).  
The PLD clamps Y-lines to ground whenever key charge is  
not being collected. The charge integrator should only receive  
charge starting just before an X line goes high, to a point just  
after the transition (the X-Y dwell time). It is an essential  
function of the PLD to neutralize charge keys during the  
negative transition of X lines; without this, charge-transfer  
would cease to function after a single X pulse, and multiple  
pulse bursts would be impossible.  
The second stage must be clamped with a low-C diode as  
shown (BAV-99 preferred) so that negative excursions of the  
amplifier do not under-drive the Ain pin of the device. An  
output resistor further limits possible Ain+ currents. Without  
clamping there can be high currents taken from Ain which can  
lead to device latchup, requiring power to be cycled to restore  
operation.  
The PLD also acts to generate a pulse that sets the dwell  
time for the QS3251 8:1 charge sampler switch. A simple  
PLD-based RC network controls the QS3251 gate pin E’  
starting from when line YG becomes active to a time after X7  
or XS transition high. XS is the logical-OR of X0..X6; X8 and  
XS are ORd together in the PLD so that any single X line can  
trigger the timing network.  
Figure 3-2 Circuit: The first opamp is a positive-gain high  
impedance configuration which amplifies the small voltage on  
Cs (C7). The reset transistor is a small-signal N-fet. C7 also  
receives charge cancellation capacitances C8 and C9. The  
R2R DAC offset is injected into the summing junction of this  
amplifier.  
X-Y dwell time can be measured with an oscilloscope by  
timing the interval from XS or X8 to 22V10 output F9. Dwell  
times of 70ns - 90ns work very well to suppress the effects of  
surface moisture films. Longer times are acceptable if such  
moisture is not anticipated.  
The second stage amplifier has a positive gain that provides  
final amplification.  
This design is simpler to implement but has lower gain than  
the circuit of Figure 3-1.  
R2 and/or C5 in Figure 3-1 should be adjusted to provide a  
timing dwell delay from the rise of an X line to the rising edge  
of Y-enable (QS3251) of around 75ns +/-20%. Shorter dwell  
times will begin to cause the suppression of human touch  
signals as well. If resistors and capacitors are used in line  
with the X and Y matrix lines for EMC and ESD suppression  
(Section 3.22), excessively short dwell times can seriously  
deteriorate signal gain. The circuit should be evaluated for the  
amount of signal loss by comparing delta signals due to touch  
both with and without the EMC circuits.  
3.11 Sample Capacitors  
Charge sampler capacitor Cs (C14 in Figure 3-1, C7 in Figure  
3-2) should be the values shown. They should be either NP0  
or C0G ceramic or PPS film for thermal stability reasons. The  
two Cz capacitors should be NP0 or C0G types only. The  
transient charge absorber C11 can be a 10% X7R type.  
More information on how the Cs and Cz capacitors function is  
described in Section 1.2.  
The values of capacitance should not be altered from the  
reference schematics; value changes can cause acquisition  
gaps to occur which can result in keys that cannot calibrate.  
R2 and C5 can be eliminated to provide the full 167ns of  
dwell time output by the QT60xx5. C5 should be replaced by  
a connection to ground, and R2 should be open-circuited.  
Source code for one type of recommended 22V10 can be  
found in Section 6. The 22V10 should have conventional  
CMOS I/O structures without bus-keepersor pullup resistors  
in order to work optimally.  
3.12 R2R Resistor Ladder  
The R2R ladder network (RN1 in Figure 3-1) should have a  
value of 100K ohms and a precision of 7 or 8 bits. The R2R  
connects to the summing junction of the first or second  
opamp depending on the circuit; it is used to offset the analog  
signal down with increasing binary input value. The R2R  
value is determined for each key during calibration by an  
algorithm that seeks to put the signal Ain+ at 2.5 volts. This  
binary value only changes when a key is recalibrated or after  
powerup during the normal startup calibration cycle; drift  
compensation does not change R2R drive.  
While the QS3251 is gated by the signal on its Epin from  
the PLD, the actual switch being controlled is determined by  
the YS0, YS1, YS2 lines from the QT60xx5.  
3.10 Opamps  
The amplifier chain should be configured as shown in Figures  
3-1 or 3-2. The opamps should have a GBW product of at  
least 2MHz, have rail-rail CMOS outputs, and be able to  
operate from split-rail supplies (split-rail capable only in the  
case of Figure 3-1). To eliminate leakage current issues the  
amplifier should be a JFET or CMOS input type only. TIs  
The R2R is driven by the matrix X lines; this is possible since  
Ain+ is only read after the completion of each burst, therefore  
this dual-use of X drive lines does not pose a conflict so long  
as these lines are not heavily loaded.  
lQ  
13  
www.qprox.com QT60xx5 / R1.05