©Quantum Research Group Ltd.
Table 1.1 Device Pin List
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
MOSI
MISO
SCK
RST
Vdd
Vss
XTO
XTI
X0
X1
X2WS
X3
X4
X5
X6
XS
Vdd
Vss
YC0
YC1
YC2
YC3
YC4
YC5
YC6
YC7
AVdd
AGnd
Aref
YS2
YS1
YS0
CZ2
CZ1
CSR
Ain
MS
Vdd
Vss
LED
DRDY
X7
YG
SS
Type
I/O PP
I/O PP
I/O PP
I
Pwr
Pwr
O
I
O
O
O
O
O
O
O
O
Pwr
Pwr
O
O
O
O
O
O
O
O
Pwr
Pwr
Pwr
O
O
O
O
O
O
I
I/O OD
Pwr
Pwr
O
O OD
O
O
IO OD
Description
Master-Out / Slave In SPI line. In Master/Slave SPI mode is used for both communication directions.
In Slave SPI mode is the data input (in only).
Master-In / Slave Out SPI line. Not used in Master/Slave SPI mode.
In Slave mode outputs data to host (out only).
SPI Clock. In Master mode is an output; in Slave mode is an input
Reset input, active low reset
+5 supply
Ground
Oscillator drive output. Connect to resonator or crystal. Can drive a charge pump circuit for Vee
supply
Oscillator drive input. Connect to resonator or crystal, or external clock source.
X0 Drive matrix scan / R2R DAC Ladder drive
X1 Drive matrix scan / R2R DAC Ladder drive
X2 Drive matrix scan / R2R DAC Ladder drive / Wake from Sleep / Sync to noise source
X3 Drive matrix scan / R2R DAC Ladder drive
X4 Drive matrix scan / R2R DAC Ladder drive
X5 Drive matrix scan / R2R DAC Ladder drive
X6 Drive matrix scan / R2R DAC Ladder drive
X summation / R2R DAC Ladder drive
+5 supply
Ground
Y 0 Line clamp control
Y 1 Line clamp control
Y 2 Line clamp control
Y 3 Line clamp control
Y 4 Line clamp control
Y 5 Line clamp control
Y 6 Line clamp control
Y 7 Line clamp control
+5 supply for analog sections
Analog ground
Analog reference, connect to Vcc
Transfer switch control bit 2
Transfer switch control bit 1
Transfer switch control bit 0
Charge cancellation drive for CZ2 capacitor
Charge cancellation drive for CZ1 capacitor
Charge integrator reset line. Active high or active low (select polarity via Setups)
Analog input from amplifier
SPI Mode / Sync out. Connect via 10k resistor to Vcc or Gnd for mode. Scope sync yields Pulse.
+5 supply
Ground
Active low LED status drive / Activity indicator
Data ready output for Slave SPI mode; active low
X7 Drive matrix scan
Y gate control to drive Y dwell timing circuit
Slave select for SPI direction control; active low
I/O:
I = Input
O = Output
Pwr = Power pin
I/O = Bi-directional line
PP = Push Pull output drive
OD = Open drain output drive
lQ
iii
www.qprox.com
QT60xx5 / R1.05
QUANTUM [ QUANTUM RESEARCH GROUP ]
