2 - CIRCUIT
SPECIFICS
A basic QT60320D circuit is
shown in Figure 2-1.
Vcc
D S 18 11
Figure 2-1 Basic QT60320D Circuit
Vcc
5 1 7 2 7 29 38
V V V V V
4
UART I N
U ART OUT
Rst
X1
X2
X3
X4
X5
X6
X7
X8
40
41
42
43
44
1
2
3
R 2R d ac 1 00K
1/4
HC4066
Keymatrix
Y4
Y3
Y2
Y1
2.1 SIGNAL PATH
USE R PO RT PINS
Q T60320
The Cs capacitor performs the
charge integration function by
collecting charge coupled
though a selected key during
the dV/dt of the rising edge of
an 'X' scan line. The charge is
sampled 'n' times during the
course of a burst of switching
cycles of length 'n'. As the
burst progresses the charge on
Cs increases in a staircase
fashion (Figure 1-4).
YS1
YS2
YS3
YS4
19
1/4
HC4066
20
1/4
HC4066
21
1/4
HC4066
22
C6 (Cz1) 8 20pF
C7 (Cz2) 8 20pF
R3 68K
_
BSN20
+
_
+
TL C22 72
R6 10K
R4 100K
8
XT1
CC 1
32
31
30
74 AC 04
7
Vcc
CAL L ED
8MHz
15
16
STAT LED
XT2
CC 2
CS
R 5 10K
L1
L2
G
AIN
37
G G G
6 18 28 39
C5 (Cs)
1 5nF
At the burst's end the voltage
on Cs, which is on the order of
a few tenths of a volt, is
amplified by a gain circuit which includes an offset current
from the R2R ladder DAC driven by the X drive lines. The
offset current from the R2R ladder repositions the output of
the amplifier chain to coincide as closely as possible with the
center span of the 60320's ADC, which can convert voltages
between 0 and 5 volts. Between bursts the Cs reset mosfet is
activated to reset the Cs capacitor to ground.
Gain is directly controlled by burst length 'n', amplifier gain
Av, and the values of Cs, Cz1 and Cz2. Only 'n' can be
adjusted on a key by key basis whereas Av and the
capacitances can only be adjusted
for all keys. The amplifier should
Figure 2-2 Improved Circuit to Suppress Water Films
typically have a total positive gain
of 100 +/- 20%..
Vcc
5 17 27 2 9 3 8
V V V V V
R st
X2
X3
X4
X5
X6
X7
X8
Vcc
D S 18 11
Keym atr ix
Y4
40
41
42
43
44
1
2
3
R 2R dac 100K
Y3
Y2
Y1
4
UAR T IN
U ART OU T
9
Rx
10
Tx
33
I1
34
I2
35
I3
36
I4
11
O1
12
O2
13
O3
14
O4
23
O5
24
O6
25
O7
26
O8
8
XT1
Q T60320
YS1
Y S2
Y S3
Y S4
19
20
21
22
C6 (Cz 1) 820pF
C 7 (Cz 2) 820p F
R 3 68 K
_
BSN 20
37
+
_
+
TLC 2272
R 6 10 K
R 4 100 K
C 5 (C s)
15nF
R 5 1 0K
Rt
E I /O
E
E
E I /O
I/O
I /O
I/O
22 V10
QS 31 25
I/O
I /O
I/O
If there is a large amount of
coupling between X and Y lines,
and where burst length 'n' is set to
a
high
number,
charge
accumulation on Cs may reach a
point where the ladder DAC can no
longer offset the signal back into
the ADC's usable range. In this
case the circuit will employ one or
two of the Cz capacitors to 'knock
back' or cancel the charge
accumulated on Cs; each Cz will
cancel charge in a discrete step as
required.
US ER PO RT PIN S
Ct
CC 1
7
8M H z
Vcc
CAL L ED
15
16
STAT LED
XT2
CC 2
CS
L1
L2
G
AIN
32
31
30
G G G
6 18 28 39
LQ
5
QT60320D R1.11/12.07.03
1/4
HC4066
1/4
HC4066
1/4
HC4066
1/4
HC4066
The QT60320D requires an
external sampling capacitor,
two Cz capacitors, an amplifier,
some analog switches, and an
R2R ladder DAC to operate.
9
Rx
10
Tx
33
I1
34
I2
35
I3
36
I4
11
O1
12
O2
13
O3
14
O4
23
O5
24
O6
25
O7
26
O8
QUANTUM [ QUANTUM RESEARCH GROUP ]
