6 Specifications
6.1 Absolute Maximum Electrical Specifications
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40OC to +105OC
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55OC to +125OC
V
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +5.5V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to (Vdd + 0.6) Volts
Eeprom setups maximum writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100,000 write cycles
6.2 Recommended operating conditions
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to 5.25V
SDuDpply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV p-p max
Cx transverse load capacitance per key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 20pF
6.3 DC Specifications
Vdd = 5.0V, Cs = 4.7nF, Rs = 470K; Ta = recommended range, unless otherwise noted
Parameter
Description
Min
Typ
Max
Units
Notes
Iddr
Vr
Vil
Vhl
Vol
Voh
Iil
Ar
Rp
Rrst
Supply current, running
Vdd internal reset voltage
Low input logic level
High input logic level
Low output voltage
25
2.9
0.8
mA
V
V
V
V
Excluding external components
2.7
2.2
0.6
4mA sink
1mA source
High output voltage
Vdd-0.7
V
Input leakage current
Acquisition resolution
Internal pullup resistors
Internal /RST pullup resistor
±1
11
50
80
µA
bits
k✡
k✡
9
20
30
DRDY, /SS pins
6.4 Timing Specifications
Parameter
Description
Burst spacing
Min
Typ
Max
Units
Notes
T
BS
500
3,000
µs
kHz
%
ns
ns
ns
ns
µs
µs
ns
ns
ns
MHz
Adjustable parameter via Setups
Fc
Fm
S1
S2
S3
S4
S5
S6
S7
S8
S9
Fck
Burst center frequency
Burst modulation, percent
È /SS to first È CLK edge
È CLK to valid MISO
Last Ç CLK to Ç /SS
Ç /SS to 3-state MISO
Ç /SS to falling DRDY
DRDY low pulse width
CLK low pulse width
CLK high pulse width
CLK period
226
±8
333
25
SPI parameter controlled by host
SPI parameter controlled by QT
SPI parameter controlled by host
SPI parameter controlled by QT
SPI parameter controlled by QT
SPI parameter controlled by QT
SPI parameter controlled by host
SPI parameter controlled by host
SPI parameter controlled by host
Max guaranteed is a min of 1.5MHz
20
20
40
1
333
333
667
1.5
SPI Clock rate
lQ
24
QT60248-AS R4.02/0405
QUANTUM [ QUANTUM RESEARCH GROUP ]
