Figure 7-1 SPI Slave Mode
Tskd
DRDY
{from QT300}
Tskh
Tskl
SCK
{from host}
SDO
{from QT300}
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Tds
Thso
Tmls
Tsosh
Figure 7-2 SPI Master Mode
Tmls
Tskd
DRDY
{from QT300}
Tskh
Tskl
SCK
{from QT300}
SDO
{from QT300}
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Tds
Tsosh
Thso
Table 7-1
Symbol
T
SKD
T
SKH
T
SKL
T
SOSH
T
HSO
T
MLS
T
DS
Parameter
Slave SPI Timing
min
25
13
12
-
7
12
12
max
-
-
-
10
-
1,000
1,000
Units
µs
µs
µs
µs
µs
µs
µs
Symbol
T
SKD
T
SKH
T
SKL
T
SOSH
T
HSO
T
MLS
T
DS
Table 7-2
Master SPI Timing
min
25
12.5
12.5
4
12.5
8.3
12.5
max
1,725
862.5
862.5
7
-
1,708
-
Units
µs
µs
µs
µs
-
µs
-
Parameter
Clock Duration
SCK High Duration
SCK Low Duration
SCK High To SDO Ready
Setup Time
SDO Hold Time
MSB-LSB Spacing
DRDY Low To SCK High
Delay
Clock Duration
SCK High Duration
SCK Low Duration
SCK High To SDO Ready
Setup Time
SDO Hold Time
MSB-LSB Spacing
DRDY Low To SCK High
Delay
LQ
9
QT300 R1.02/0204
QUANTUM [ QUANTUM RESEARCH GROUP ]
