time-slot. Within these ICs the sensing channels already
operate in time-sequence, so it is not possible for a given
IC’s channels to cross interfere with each other even if the
electrodes are directly adjacent to one another.
However the use of 2 or more chips can create a problem,
because if they are not somehow synchronized to each other
the cross-interference problem will occur between adjacent
channels of the different chips.
3 - CIRCUIT GUIDELINES
3.1 SAMPLE CAPACITOR
Charge sampler caps Cs can be virtually any plastic film or
low to medium-K ceramic capacitor. The acceptable Cs
range is from 1nF to 200nF depending on the sensitivity
required; larger values of Cs demand higher stability to
ensure reliable sensing. Acceptable capacitor types include
plastic film (especially PPS film), NP0 / C0G ceramic. X7R
ceramic can also be used but these are less stable over
temperature.
2.4.1 M
ULTI
-C
HIP
S
YNC
A bidrectional, open-drain SYNC pin has been provided to
allow 2 or more QT140’s or QT150’s in various combinations
to synchronize to each other (Figure 1-8). All the chips in a
system, whether 1 or 20, should connect to this common line
with a single 10K pullup resistor.
A single QT140 or QT150 must also use a pullup resistor.
SYNC floats high during the Channel 1 sensing burst. When
the IC completes Channel 1 sensing, it pulls down SYNC.
SYNC will continue to be pulled low until the last sensing
channel has completed, when it is unclamped. The IC waits
until SYNC rises high before it will start Channel 1 sensing
again.
If two or more chips are tied into SYNC, all chips must
release SYNC before it actually floats high. Thus, all chips
that us a common SYNC connection will synchronize on
Channel 1.
This mechanism forces all like sensing channels to be
time-aligned among all chips. Thus, all Channel 1’s acquire
at the same time, then all Channel 2’s etc. This means that
when designing a PCB and electrode array, it is important to
not place like channel numbers next to each other or they will
cross interfere. However this leaves a tremendous latitude
for placing channels from different chips having different
channel numbers next to each other.
For example Channel 1 of chip ‘A’ can be routed and
physically placed adjacent to Channel 2 of chip ‘B’, or
Channel 4 of chip ‘F’ and so on. But it is not good to place
Channel 3 of chip ‘A’ next to Channel 3 of chip ‘B’.
3.2 OPTION STRAPPING
The option pins OC, AKS, OPT1 and OPT2 should never be
left floating. If they are floated, the device can draw excess
power and the options will not be properly read. See Section
2.2 and 2.3 for options.
3.3 POWER SUPPLY, PCB LAYOUT
The power supply can range from 3 to 5.5 volts. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shift
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The devices will track slow changes in Vdd, but can be
seriously affected by rapid voltage steps.
If the supply is shared with another electronic system, care
should be taken to assure that the supply is free of digital
spikes, sags, and surges which can cause adverse effects.
The supply is best locally regulated using a conventional
78L05 type regulator, or almost any 3-terminal LDO device
from 3V to 5V.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss; the bypass cap should
be placed very close to the device Vss and Vdd pins.
The PCB should if possible include a copper pour under and
around the IC, but not extensively under the SNS lines.
2.4.2 N
OISE
S
YNC
The effects of external noise sources can be heavily
suppressed by synchronizing these devices to the noise
source itself. External noise creates an ‘aliasing’ or ‘beat’
frequency effect between the sampling rate of the QT part
and the external noise frequency.
In many cases, especially with repetitive noise like 50/60Hz
AC fields, the noise effects will vanish if the device is
synchronized to the external field. This can take the form of a
simple AC zero-crossing detector feeding the pullup resistor
on SYNC instead of tying the SYNC resistor to Vdd. Multiple
devices tied to SYNC can be synchronized to the mains
frequency in this fashion.
In the case of noise from sources such as backlight inverters
etc, it is sometimes best to synchronize by disabling the
inverter for a brief moment while the QT device acquires.
3.4 OSCILLATOR
The oscillator should be a 10MHz resonator with ceramic
capacitors to ground on each side. 3-pin resonators with
built-in capacitors designed for the purpose are inexpensive
and commonly found. Manufacturers include AVX, Murata,
Panasonic, etc.
Alternatively an external clock source can be used in lieu of a
resonator. The OSC_I pin should be connected to the
external clock, and OSC_O should be left unconnected.
These ICs are fully synchronous devices that are slaved to
the OSC_I clock frequency. If the frequency of OSC_I is
changed, all timings will also change in direct proportion,
from the charge and transfer times to the detection response
times and the Max On-duration timings.
3.5 UNUSED CHANNELS
Unused SNS pins should not be left open. They should have
a small value non-critical dummy Cs capacitor connected to
their SNS pins to allow the internal circuit to continue to
function properly. A nominal value of 1nF (1,000pF) X7R
ceramic will suffice.
lQ
8
QT140/150 1.01/1102
QUANTUM [ QUANTUM RESEARCH GROUP ]
