1 - OVERVIEW
Figure 1-1 Basic Circuit Configuration
+2.5 to 5
SENSING
ELECTRODE
The QT113 is a digital burst mode charge-transfer (QT)
sensor designed specifically for touch controls; it includes all
hardware and signal processing functions necessary to
provide stable sensing under a wide variety of changing
conditions. Only a single low cost, non-critical capacitor is
required for operation.
Figure 1-1 shows a basic circuit using the device.
1
2
3
4
OUTPUT=DC
TIMEOUT=10 Secs
TOGGLE=OFF
GAIN=HIGH
Vdd
OUT
SNS2
7
5
6
C
s
R
SERIES
1.1 BASIC OPERATION
The QT113 employs bursts of charge-transfer cycles to
acquire its signal. Burst mode permits power consumption in
the microamp range, dramatically reduces RF emissions,
lowers susceptibility to EMI, and yet permits excellent
response time. Internally the signals are digitally processed
to reject impulse noise, using a 'consensus' filter which
requires three consecutive confirmations of a detection
before the output is activated.
The QT switches and charge measurement hardware
functions are all internal to the QT113 (Figure 1-2). A 14-bit
single-slope switched capacitor ADC includes both the
required QT charge and transfer switches in a configuration
that provides direct ADC conversion. The ADC is designed to
dynamically optimize the QT burst length according to the
rate of charge buildup on Cs, which in turn depends on the
values of Cs, Cx, and Vdd. Vdd is used as the charge
reference voltage. Larger values of Cx cause the charge
transferred into Cs to rise more rapidly, reducing available
resolution; as a minimum resolution is required for proper
operation, this can result in dramatically reduced apparent
gain. Conversely, larger values of Cs reduce the rise of
differential voltage across it, increasing available resolution
by permitting longer QT bursts. The value of Cs can thus be
increased to allow larger values of Cx to be tolerated (Figures
4-1, 4-2, 4-3 in Specifications, rear).
The IC is responsive to both Cx and Cs, and changes in Cs
can result in substantial changes in sensor gain.
Option pins allow the selection or alteration of several special
features and sensitivity.
OPT1
GAIN
10nF
C
x
OPT2
Vss
SNS1
8
1.2 ELECTRODE DRIVE
The internal ADC treats Cs as a floating transfer capacitor; as
a result, the sense electrode can in theory be connected to
either SNS1 or SNS2 with no performance difference.
However the electrode should only be connected to pin SNS2
for optimum noise immunity.
In all cases the rule Cs >> Cx must be observed for proper
operation; a typical load capacitance (Cx) ranges from
10-20pF while Cs is usually around 10-50nF.
Increasing amounts of Cx destroy gain; therefore it is
important to limit the amount of stray capacitance on both
SNS terminals, for example by minimizing trace lengths and
widths and keeping these traces away from power or ground
traces or copper pours.
The traces and any components associated with SNS1 and
SNS2 will become touch sensitive and should be treated with
caution to limit the touch area to the desired location.
A series resistor, Rseries, should be placed inline with the
SNS2 pin to the electrode to suppress ESD and EMC effects.
1.3 ELECTRODE DESIGN
1.3.1 E
LECTRODE
G
EOMETRY AND
S
IZE
There is no restriction on the shape of
the electrode; in most cases common
sense and a little experimentation can
result in a good electrode design. The
QT113 will operate equally well with
long, thin electrodes as with round or
square ones; even random shapes are
acceptable. The electrode can also be
a 3-dimensional surface or object.
Sensitivity is related to electrode
surface area, orientation with respect
to the object being sensed, object
composition, and the ground coupling
quality of both the sensor circuit and
the sensed object.
If a relatively large electrode surface is
desired, and if tests show that the
electrode has more capacitance than
the QT113 can tolerate, the electrode
can be made into a sparse mesh
(Figure 1-3) having lower Cx than a
Figure 1-2 Internal Switching & Timing
R esult
Single-Slo pe 14-bit
Switched Capacitor ADC
E LE C TRO DE
S NS 2
Burst Controller
C
s
C
x
S NS 1
S tart
Do ne
C ha rge
Amp
lQ
2
R1.05/0405
QUANTUM [ QUANTUM RESEARCH GROUP ]
