Figure 1.2 Connection Diagram - Simplified Mode (32-QFN Package)
SMR resistor installed between SNS6K, SNS7
Vunreg
4.7uF
+2.8 ~ +5V
Voltage Reg
4.7uF
*100nF
VDD
3
R
S3
12
R
SNS3
4.7nF
C
S3
R
S4
4.7nF
C
S4
R
S5
16
4.7nF
C
S5
R
S6
18
4.7nF
C
S6
R
S7
4.7nF
C
S7
R
S8
25
4.7nF
C
S8
R
S9
27
4.7nF
C
S9
2.2K
28
2.2K
26
2.2K
2.2K
SMR
1M
20
21
19
2.2K
17
2.2K
2.2K
2
VDD
SNS3
SNS3K
SNS4
/RST
SNS2K
SNS2
SNS1K
SNS1
SNS0K
SNS0
11
R
S2
10
9
8
7
1M
6
AKS_0
Vdd / Vss
2.2K
R
S0
2.2K
R
S1
4.7nF
C
S2
4.7nF
C
S1
4.7nF
C
S0
2.2K
R
SNS2
KEY 2
10K
R
SNS1
KEY 3
10K
R
SNS4
13
KEY 1
10K
R
SNS0
KEY 4
10K
R
SNS5
15
SNS4K
SNS5
SNS5K
SNS6
SNS6K
SNS7
SNS7K
SNS8
SNS8K
SNS9
SNS9K
KEY 0
10K
KEY 5
10K
R
SNS6
KEY 6
10K
R
SNS7
QT1101
32-QFN
Rb1
VDD
Recommended Rb1, Rb2 Values
With Spread-Spectrum
Vdd Range
Rb1 Rb2
2.8 ~ 2.99V 12K 27K
3.0 ~ 3.59V 12K 22K
3.6 ~ 5V 15K 27K
No Spread-Spectrum
Vdd Range
Rb1 Rb2
2.8 ~ 2.99V 15K
dni
3.0 ~ 3.59V 18K
dni
3.6 ~ 5V 20K
dni
dni = do not install
KEY 7
10K
R
SNS8
OSC
4
Rb2
KEY 8
10K
R
SNS9
KEY 9
10K
Css
SS
1
100nF
No Spread-spectrum:
Replace Css with 100K resistor
100K
RX
LP IN
23
32
100K
31
100K
30
29
5
Vdd
Vdd
Vdd
2W DATA
DATA
/CHANGE
SYNC/LP
1W
/CHANGE
DETECT OUT
24
DETECT
N.C.
N.C.
VSS
22
Table 1.6
AKS Resistor Options
AKS_0
Vss
Vdd
AKS MODE
Off
On, global
FAST-DETECT
Enabled
Off
Table 1.7
Functions in Simplified Mode
SYNC/LP pin
Max on-duration delay
Detect Pin
200ms LP function; sync not available
60 seconds
Push-pull, active high
Lq
5
QT1101 R4.06/0806
QUANTUM [ QUANTUM RESEARCH GROUP ]
