Figure 1.2 UART / Scanport Connection Diagram
Shown with optional EEPROM
Regulator
VUNREG
VI
VO
VDD
*100nF
G
*One bypass capacitor to be tightly coupled to pins 36 and 17.
Follow regulator manufacturer's recommendations
for input and output capacitors.
*10uF
*4.7uF
QT1100A-AS
4.7K
4.7K
4.7K
2.2K
2.2K
2.2K
2.2K
2.2K
22nF
22nF
22nF
22nF
22nF
2.2K
KEY2
KEY1
KEY0
4.7K
22nF
KEY3
KEY4
KEY5
KEY6
KEY7
2.2K
4.7K
4.7K
4.7K
4.7K
22nF
2.2K
22nF
VDD
12MHz 3-PIN
RESONATOR
2.2K
2.2K
22K
22nF
22nF
4.7K
4.7K
RESET
4.7K
KEY8
KEY9
SYNC
22K
VSS
DOUT
DIN
CLK
CS
SCANI_0
SCANI_1
SCANI_2
SCANO_3
SCANO_2
SCANO_1
SCANO_0
5
6
7
8
4
NC
3
NC
2
1
VDD
93LC46A
10K
TX
10K
22K
CRDY
RX/WAKE
Note 1: EEPROM is optional when using UART interface in this drawing.
Note 2: UART interface is not normally used when using Scanport interface and vice versa.
Note 3: See Table 1.1 for unused pin connections
LQ
10
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105
QUANTUM [ QUANTUM RESEARCH GROUP ]
