Figure 1.2 Connection Diagram - Simplified Mode
Vunreg
*4.7uF
+2.8 ~ +5V
Voltage Reg
*4.7uF
*100nF
VDD
* Note: one bypass capacitor to be tightly wired
between Vdd and Vss. Follow manufacturer’s
recommendations for input and output capacitors.
Keep these parts
close to the IC
1nF
12
3
2
Keep these parts
close to the IC
SNS2K
SNS2
SNS1K
SNS1
SNS0K
SNS0
11
10
9
8
7
6
VDD
SNS3
SNS3K
SNS4
/RST
1nF
C
S2
1nF
R
SNS2
KEY 2
10K
R
SNS1
KEY 1
R
SNS3
KEY 3
10K
C
S3
1nF
C
S4
13
R
SNS4
KEY 4
10K
R
SNS5
KEY 5
10K
R
SNS6
KEY 6
10K
15
SNS4K
SNS5
SNS5K
SNS6
SNS6K
1nF
16
C
S5
1nF
C
S6
17
18
19
10K
C
S1
R
SNS0
1nF
C
S0
10K
AKS_0
Vdd / Vss
KEY 0
1M
VDD
Recommended Rb1, Rb2 Values
Vdd Range
Rb1 Rb2
2.8 ~ 3.59V 12K
22K
3.6 ~ 5V 15K
27K
The required value of spread-spectrum capacitor CSS
will vary according to the lengths of the acquire bursts,
see Section 3.2. A typical value of CSS is 100nF.
C
SS
SMR
1M
20
Rb1
R
SNS7
KEY 7
10K
1nF
C
S7
21
SNS7
SNS7K
QT1081
32-QFN
OSC
4
Rb2
SS
1
OUT_7
32
22
OUT_7
OUT_6
OUT_5
OUT_4
OUT_3
OUT_2
OUT_1
OUT_0
VSS
OUT_6
31
OUT_5
30
LP IN
DETECT OUT
23
OUT_4
SYNC/LP
DETECT
OUT_3
OUT_2
OUT_1
OUT_0
29
28
27
26
25
24
Table 1.6
AKS Resistor Options
AKS_0
Vss
Vdd
AKS MODE
Off
On, global
FAST-DETECT
Enabled
Off
Table 1.7
Functions in Simplified Mode
Function
Output Drive, Polarity
SYNC/LP pin
Max on-duration delay
Detect Pin
Parameter
One-per-key outputs, push-pull, active high
180ms nom LP function; sync not available
60 seconds (nom)
Active high on any detect
lQ
7
QT1081_1R0.04_0307
QUANTUM [ QUANTUM RESEARCH GROUP ]
