2 Wiring and Parts
2.1 Application Note
Refer to Application Note AN-KD02, downloadable from the
Quantum website for more information on construction and
design methods. Go to http://www.qprox.com, click the
Support tab and then Application Notes.
If desired, the supply can be regulated using a Low Dropout
(LDO) regulator. See Application Note AN-KD02 (see
Section 2.1) for further information on power supply
considerations.
Suggested regulator manufacturers:
•
•
•
Toko (XC6215 series)
Seiko (S817 series)
BCDSemi (AP2121 series)
2.2 Cs Sample Capacitor
Cs is the charge sensing sample capacitor. The required Cs
value depends on the thickness of the panel and its dielectric
constant. Thicker panels require larger values of Cs. Typical
values are 1nF to 50nF depending on the sensitivity required;
larger values of Cs demand higher stability and better
dielectric to ensure reliable sensing.
The Cs capacitor should be a stable type, such as X7R
ceramic or PPS film. For more consistent sensing from unit to
unit, 5 percent tolerance capacitors are recommended. X7R
ceramic types can be obtained in 5 percent tolerance at little
or no extra cost. In applications where high sensitivity (long
burst length) is required the use of PPS capacitors is
recommended.
Parts placement:
The chip should be placed to minimize the
SNSK trace length to reduce low frequency pickup, and to
reduce Cx which degrades gain. The Cs and Rs resistors (see
Figure 2.1) should be placed as close to the body of the chip
as possible so that the trace between Rs and the SNSK pin is
very short, thereby reducing the antenna-like ability of this
trace to pick up high frequency signals and feed them directly
into the chip. A ground plane can be used under the chip and
the associated discretes, but the trace from the Rs resistor
and the electrode should not run near ground, to reduce
loading.
For best EMC performance the circuit should be made entirely
with SMT components.
Electrode trace routing:
Keep the electrode trace (and the
electrode itself) away from other signal, power, and ground
traces including over or next to ground planes. Adjacent
switching signals can induce noise onto the sensing signal;
any adjacent trace or ground plane next to, or under, the
electrode trace will cause an increase in Cx load and
desensitize the device.
Important Note: for proper operation a 100nF (0.1µF)
ceramic bypass capacitor must be used directly between
V
DD
and V
SS
, to prevent latch-up if there are substantial
V
DD
transients; for example, during an ESD event. The
bypass capacitor should be placed very close to the
device’s power pins.
2.3 Rs Resistor
Series resistor Rs is in line with the electrode connection and
should be used to limit ESD currents and to suppress radio
frequency interference (RFI). It should be approximately
4.7k to 33k .
Although this resistor may be omitted, the device may become
susceptible to external noise or RFI. For details of how to
select these resistors see the Application Note AN-KD02
(Section 2.1).
2.4 Power Supply, PCB Layout
The power supply can range between 2.0V and 5.5V. If the
power supply is shared with another electronic system, care
should be taken to ensure that the supply is free of digital
spikes, sags, and surges which can adversely affect the
device. The QT102 will track slow changes in V
DD
, but it can
be badly affected by rapid voltage fluctuations. It is highly
recommended that a separate voltage regulator be used just
for the QT102 to isolate it from power supply shifts caused by
other components.
lQ
5
QT102_2R3.04_0807
QUANTUM [ QUANTUM RESEARCH GROUP ]
