QN8007B/8007LB
Table 1: Pin Descriptions
PINS
NAME
DESCRIPTION
1
2
N/C
N/C
No connect
No connect
3
AUGND
ALI
Audio ground
4
Analog audio input – left channel
Analog audio input – right channel
Analog ground
5
ARI
6
AGND
RFI
7
Receiver RF input
RF ground
8
RFGND
RFO
9
Transmitter RF output – connect to matched antenna.
IO voltage – specifies voltage limit for all digital pins.
10
VIO
Chip enable: Chip power down if less than 0.6V, (see also MOD pin below)
power up if voltage applied >min (0.7*VIO, 1.8V).
11
12
CEN
Bus mode: HIGH = 3-wire serial operation. LOW = 2-wire serial operation
Note: Both MOD=0 and CEN=0 to disable chip.
MOD
13
14
15
16
MCK
INT
Master clock – for digital audio interface.
Interrupt
Word select (I2S mode only)
WS
XCLK
External clock input (register 49h, bit 4 must be HIGH)
On-chip crystal driver port 1.
If using an external clock source, connect this pin to ground.
17
18
XTAL1
XTAL2
On-chip crystal driver port 2.
If using an external clock source, connect this pin to ground.
19
20
AGND
DIN
Analog ground
Data in (I2S mode only)
Serves as the bus enable pin in 3-wire serial mode; serves as the address select pin in
2-wire serial mode, SEB = Low for default address, SEB = High for register controlled
address.
21
SEB
22
23
24
25
SCL
SDA
VCC
PAD
Clock for 2-wire or 3-wire serial bus.
Bi-directional data line for 2- or 3-wire serial bus.
Voltage supply
Exposed pad, must be soldered to the ground on the PCB.
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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QUANTUM [ QUANTUM RESEARCH GROUP ]
