QN8006B/8006LB
Word: GAIN_TXPLT Address: 0Fh
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
i2sundfl_
clr
i2sovfl_
clr
gain_txpl
[3]
gain_txplt
[2]
gain_txplt
[1]
gain_txplt
[0]
rds_int_en
cca_int_en
wo
wo
wo
wo
wo
wo
wo
wo
Bit
Symbol
Default
Description
7
I2SUNDFL_
CLR
0
I2S buffer underflow clear: User has to de-assert this bit after clearing.
0
No action
1
Clear
6
I2SOVFL_
CLR
0
I2S buffer overflow clear: User has to de-assert this bit after clearing.
0
1
No action
Clear
5:2
GAIN_TXPLT
[3:0]
10 01
Gain of TX pilot to adjust pilot frequency deviation: Refer to peak frequency
deviation of MPX signal when audio input is full scale.
0111
1000
1001
1010
7% * 75kHz
8% * 75kHz
9% * 75kHz
10% * 75kHz
1
RDS_INT_EN
0
RDS RX/TX Interrupt Enable: When RDS_INT_EN=1, a 4.5ms low pulse
will be output from DIN/INT (RX mode) or DOUT/INT (TX mode) when a
new group of data in RDSD0~RDSD7 is loaded into the internal transmitting
buffer after user toggles RDSTXRDY (TX mode) or a new group of data is
received and stored into RDS0~RDS7 (RX mode).
0
1
Disable
Enable
0
CCA_INT_EN
0
TX CCA / RX CCA Interrupt Enable: When CCA_INT_EN=1, a 4.5ms low
pulse will be output from DIN/INT (RX mode) or DOUT/INT (TX mode)
when TXCCA (TX mode) or a RXCCA (RX mode) is finished.
0
1
Disable
Enable
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
Page 43
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