QN8006B/8006LB
Word: REG_VGA
Address: 04h
Bit 7
Bit 6
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
(LSB)
xcsel[0]
wo
rin[1]
wo
rin[0]
wo
xcsel[5]
wo
xcsel[4]
wo
xcsel[3]
wo
xcsel[2]
wo
xcsel[1]
wo
Bit
Symbol
Default
Description
7:6
RIN[1:0]
01
TX mode input impedance for both L/R channels: (kΩ)
0 0
0 1
1 0
1 1
10
20
40
80
Crystal cap load setting: The loading cap on each side is:
10+XCSEL*0.32 pF, i.e. it ranges from 10pF to 30pF. Default is 20 pF.
5:0
XCSEL[5:0]
10 0000
Word: CIDR1
Address: 05h (RO)
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
rsvd
ro
rsvd
ro
rsvd
ro
cid1[2]
ro
cid1[1]
ro
cid1[0]
ro
cid2[1]
ro
cid2[0]
ro
Bit
7:5
4:2
Symbol
Rsvd
value
Description
rrr
rrr
reserved
CID1[2:0]
Chip ID for product family:
000 FM
000
001-111 Reserved
1:0
CID2[1:0]
rr
Chip ID for minor revision:
00
00
01
10
11
0
1
2
3
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
Page 36
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
QUANTUM [ QUANTUM RESEARCH GROUP ]
