Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 29
SPD codes for HYS[64/72]T256020EU–3.7–B
Product Type
Organization
HYS64T256020EU–3.7–B HYS72T256020EU–3.7–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–4200U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–4200E–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
3D
50
00
82
08
00
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
80
08
08
0E
0A
61
48
00
05
3D
50
02
82
08
08
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
Rev. 1.0, 2006-10
51
10262006-SX8C-DEY8