Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2
Pin Configurations
2.1
Chip Configuration
The chip configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 2 (200 balls). The abbreviations
used in columns Ball and Buffer Type are explained in Table 3 and Table 4 respectively. The Ball numbering is depicted in
Figure 1.
TABLE 5
Chip Configuration of SO-DIMM
Ball No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
30
CK0
CK1
CK0
CK1
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Signals 2:0, Complement Clock Signals 2:0
164
32
I
I
166
79
I
I
Clock Enable Rank 1:0
Note: 2 Ranks module
80
I
NC
Not Connected
Note: 1-rank module
Control Signals
110
115
S0
S1
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
I
NC
Not Connected
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
108
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
113
109
Address Signals
107
106
85
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
SSTL
Less than 1Gb DDR2 SDRAMS
Rev. 1.1, 2007-01
6
08212006-PKYN-2H1B
QIMONDA [ QIMONDA AG ]
