Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
HYS64T128021EDL–3–B2 HYS64T128921EDL–3–B2
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
PC2–5300S–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300S–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
RAS.MIN [ns]
Module Density per Rank
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
t
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
50
7A
53
34
36
27
4C
2A
4C
20
25
00
00
00
00
12
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
50
7A
53
34
36
27
4C
2A
4C
20
25
00
00
00
00
12
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Rev. 1.1, 2007-01
59
08212006-PKYN-2H1B
QIMONDA [ QIMONDA AG ]
