Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
1 Rank
1 Rank
1 Rank
1 Rank
(×16)
(×16)
(×8)
(×8)
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
PLL Relock Time
00
53
72
53
2B
1D
1D
23
16
36
1C
30
00
00
00
00
11
BA
7F
7F
7F
7F
7F
51
00
53
72
53
2B
1D
1D
23
16
36
1C
30
00
00
00
00
12
BD
7F
7F
7F
7F
7F
51
00
51
78
3F
2E
1E
1E
24
17
34
1E
20
00
00
00
00
11
D0
7F
7F
7F
7F
7F
51
00
51
78
3F
2E
1E
1E
24
17
34
1E
20
00
00
00
00
12
D3
7F
7F
7F
7F
7F
51
00
51
78
3F
2E
1E
1E
24
17
34
1E
20
00
00
00
00
11
E2
7F
7F
7F
7F
7F
51
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Rev. 1.41, 2007-05
54
03292006-EZUJ-JY4S