HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM Table 4
DIMM is listed by function in Table 4 (184 pins). The
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
abbreviations used in columns Pin and Buffer Type are
explained in Table 5 and Table 6 respectively. The pin
numbering is depicted in Figure 1.
Type Type
122 A8
27 A9
I
I
I
I
I
I
SSTL Address Bus 11:0
SSTL
141 A10
AP
SSTL
Table 4
Pin Configuration of UDIMM
SSTL
Pin# Name Pin Buffer Function
Type Type
118 A11
115 A12
SSTL
SSTL Address Signal 12
Clock Signals
Note:Module based on
256 Mbit or larger
dies
137 CK0
NC
I
SSTL Clock Signals 2:0
NC
—
16
76
CK1
CK2
I
SSTL
NC
NC
I
—
Note:128 Mbit based
module
I
SSTL
138 CK0
NC
I
SSTL Complement Clock
167 A13
SSTL Address Signal 13
Signals 2:0
NC
—
Note:1 Gbit based
module
17
75
21
CK1
I
I
I
I
SSTL
SSTL
CK2
NC
NC
—
Note:Module based on
512 Mbit or
CKE0
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note: 2-rank module
smaller dies
111 CKE1
Data Signals
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
NC
NC
—
Note: 1-rank module
4
Control Signals
6
SSTL
157 S0
158 S1
I
I
SSTL Chip Select Rank 0
SSTL Chip Select Rank 1
Note: 2-rank module
8
SSTL
94
95
98
99
12
13
19
20
SSTL
SSTL
NC
NC
—
Note: 1-rank module
SSTL
154 RAS
I
I
SSTL Row Address Strobe
SSTL
65
CAS
SSTL Column Address
Strobe
SSTL
63
WE
I
SSTL Write Enable
SSTL
Address Signals
DQ10 I/O
DQ11 I/O
SSTL
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
SSTL Bank Address Bus
SSTL
2:0
SSTL
105 DQ12 I/O
106 DQ13 I/O
109 DQ14 I/O
110 DQ15 I/O
SSTL
SSTL Address Bus 11:0
SSTL
A1
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
A2
SSTL
130 A3
23
24
28
31
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
SSTL
37
32
A4
A5
SSTL
SSTL
125 A6
29 A7
SSTL
114 DQ20 I/O
117 DQ21 I/O
SSTL
SSTL
Internet Data Sheet
5
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
QIMONDA [ QIMONDA AG ]
