Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 14
HYS[64/72]D[32/64/128]3xxHU-5-B
Product Type
Organization
256MB
512MB
512MB
1 GByte 1 GByte
×64 ×72
2 Ranks 2 Ranks
×64
×64
×72
1 Rank
1 Rank
1 Rank
(×16)
(×8)
(×8)
(×8) (×8)
Label Code
PC3200U PC3200U PC3200U PC3200U PC3200U
–30331 –30330 –30330 –30330 –30330
JEDEC SPD Revision
Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
40
00
04
50
50
00
82
10
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
01
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
01
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
02
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.22, 2007-01
28
03292006-CXBY-V2JX