Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Parameter
Symbol
–5
–6
Unit
Note1) / Test
Condition
DDR400B
DDR333
Min.
Max.
Min.
Max.
Address and control input hold time
tIH
0.6
—
0.75
—
ns
ns
Fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
Slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Read preamble
tRPRE
tRPST
tRAS
tRC
0.9
0.40
40
1.1
0.9
0.40
42
1.1
tCK
tCK
ns
ns
Read postamble
0.60
70E+3
—
0.60
70E+3
—
Active to Precharge command
Active to Active/Auto-refresh command
period
55
60
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC
70
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
tRCD
tRP
15
15
—
—
18
18
—
—
ns
ns
ns
ns
ns
tCK
tRAP
tRCD – tRASmin
Active bank A to Active bank B command tRRD
Write recovery time tWR
10
15
—
—
—
—
12
15
—
—
—
—
Auto precharge write recovery + precharge tDAL
time
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tWTR
tXSNR
tXSRD
tREFI
2
—
—
—
7.8
1
—
—
—
7.8
tCK
ns
2)3)4)5)
75
200
—
75
200
—
2)3)4)5)
tCK
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.22, 2007-01
17
03292006-CXBY-V2JX
QIMONDA [ QIMONDA AG ]
