Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
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TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command, see
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
1
2
4
8
111B Full Page (Sequential burst type only)
BT
CL
3
w
w
Burst Type
See Table 6 for internal address sequence of low order address bits.
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
Mode
[12:7]
w
Operation Mode
Note: All other bit combinations are RESERVED.
0B
1B
Burst read/burst write
Burst read/single write
Rev. 1.52, 2007-06
10
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
