Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
Parameter
Symbol
–7.5
Unit Note1)2)3)
PC133–333
Min.
Max.
Write Cycle
8)
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
15
—
0
—
—
—
ns
tCK
tCK
9)
Last Data Input to Activate
(Write with Auto Precharge)
tDAL(min.)
tDQW
DQM Write Mask Latency
1) TA = 0 to 70 °C for HYB..., TA = -40 to 85 °C for i-temp part (HYI..); VSS = 0 V, VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK
greater or equal the specified tWR value, where tck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
FIGURE 2
Measurement conditions for tAC and tOH
t C H
2.4 V
0.4 V
1.4 V
C LO C K
tT
tC L
t IH
tIS
IN P U T
1.4 V
tAC
tAC
t LZ
t O H
O U TP U T
1.4 V
t H Z
IO.vsd
Rev. 1.52, 2007-06
16
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
