Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
2
Configuration
This chapter contains the chip configuration and block diagrams.
2.1
Configuration for TFBGA-60
The ball configuration of a DDR SDRAM is listed by function in Table 3. The abbreviations used in the Ball#/Buffer Type column
are explained in Table 4 and Table 5 respectively.
TABLE 3
Configuration
Ball#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2
CK1
CK1
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3
Complementary Clock Signal
Clock Enable
H3
Control Signals
H7
G8
G7
H8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
J8
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus
Address Bus
J7
BA1
A0
K7
L8
L7
M8
M2
L3
L2
K3
K2
J3
A1
A2
A3
A4
A5
A6
A7
A8
A9
K8
A10
AP
A11
A12
J2
H2
Rev. 1.10, 2008-05
6
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
