Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
Features
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Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Programmable CAS latency: 2, 2.5, 3 and 4
Programmable burst lengths: 2, 4, or 8
Programmable drive strength: normal, weak
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 μs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
• VDD = 2.5 V ± 0.2 V, VDD = 2.6 V ± 0.1 V (DDR500)
• VDDQ = 2.5 V ± 0.2 V, VDDQ = 2.6 V ± 0.1 V (DDR500)
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Packages: PG-TSOPII-66, PG-TFBGA-60
RoHS Compliant Products1)
TABLE 1
Performance
Part Number Speed Code
–4
–5A
–5
–6
Unit
Speed Grade
DDR500B
250
DDR400A
200
DDR400B
200
DDR333B
166
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Max. Clock Frequency
@CL4
@CL3
@CL2.5
@CL2
fCK4
fCK3
fCK2.5
fCK2
MHz
MHz
MHz
MHz
250
200
200
166
200
200
166
166
133
133
133
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
For more information please visit www.qimonda.com/green_products.
Rev. 1.10, 2008-05
3
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
