Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
A7, F8, M7
VDD
PWR
PWR
—
—
Power Supply
Power Supply
A1, B8, C2, D8, VSSQ
E2
A3, F2, M3
VSS
PWR
—
—
Power Supply
Not Connected
Not Connected ×8 Organization
B1, B9, C1, C9, NC
D1, D9, E1, E7,
E9, F7, F9
NC
Not Connected ×16 Organization
F9
NC
NC
—
Not Connected
TABLE 4
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
Output. Digital levels
I/O is a bidirectional input/output signal
Input. Analog levels
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
Rev. 1.10, 2008-05
8
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
