Internet Data Sheet
HYI25DC256[16/80]0CE
256 Mbit Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 3 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 4 and Table 5 respectively.
TABLE 3
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
45
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal
46
CK
Complementary Clock Signal
Clock Enable
44
CKE
Control Signals
23
22
21
24
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
26
27
29
30
31
32
35
36
37
38
39
40
28
BA0
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Bank Address Bus 2:0
Address Bus 11:0
BA1
A0
I
I
A1
I
A2
I
A3
I
A4
I
A5
I
A6
I
A7
I
A8
I
A9
I
A10
AP
A11
A12
NC
I
I
41
42
17
I
I
NC
Address Signal 13
Note: 512 Mbit or smaller dies
Rev. 1.00, 2006-09
5
03292006-O26P-394X
QIMONDA [ QIMONDA AG ]
