Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
2
Configuration
This chapter contains the chip configuration and block diagrams.
2.1
Configuration for TSOPII-66
The pin configuration of a DDR SDRAM is listed by function in Table 4. The abbreviations used in the Pin#/Buffer Type column
are explained in Table 5 and Table 6 respectively.
TABLE 4
Configuration
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
45
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal
46
CK
Complementary Clock Signal
Clock Enable
44
CKE
Control Signals
23
22
21
24
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
26
27
29
30
31
32
35
36
37
38
39
40
28
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus
Address Bus
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
41
42
Rev. 1.41, 2007-12
7
03292006-3TFJ-HNV3
Date: 2007-12-13
QIMONDA [ QIMONDA AG ]
