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HYI25D256800CF-5 参数 Datasheet PDF下载

HYI25D256800CF-5图片预览
型号: HYI25D256800CF-5
PDF下载: 下载PDF文件 查看货源
内容描述: 256 - Mbit的双数据速率SDRAM [256-Mbit Double-Data-Rate SDRAM]
分类和应用: 动态存储器
文件页数/大小: 39 页 / 2092 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)  
256 Mbit Double-Data-Rate SDRAM  
Parameter  
Symbol –7  
DDR266A  
Unit  
Note/Test  
Condition1)  
Min.  
Max.  
2)3)4)5)13)  
2)3)4)5)  
Exit self-refresh to non-read command  
Exit self-refresh to read command  
tXSNR  
tXSRD  
75  
ns  
200  
tCK  
1)  
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C TA 70 °C  
2) Input slew rate 1 V/ns  
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals  
other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns.  
4) Inputs are not recognized as valid until VREF stabilizes.  
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT  
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.  
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific  
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).  
8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured  
between VIH(ac) and VIL(ac)  
.
t
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.  
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.  
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition  
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the  
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from  
HIGH to LOW at this time, depending on tDQSS  
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system  
performance (bus turnaround) degrades accordingly.  
13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK  
Rev. 2.3, 2007-03  
30  
03062006-8CCM-VPUW  
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