Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2.3
Chip Configuration for PG-TFBGA-92
The chip configuration of a DDR2 SDRAM is listed by function in Table 13. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 14 and Table 15 respectively.
TABLE 13
Chip Configuration of DDR SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
M8
N8
N2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
CK
CKE
Control Signals ×16 Organization
N7
P7
N3
P8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
P2
P3
P1
R8
R3
R7
T2
T8
T3
T7
U2
U8
U3
R2
BA0
BA1
BA2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Note: 1 Gbit components and higher
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
U7
V2
Rev. 1.3, 2007-07
18
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
