Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 1
Ball Configuration for ×4 components, PG-TFBGA-68 (top view)
ꢃ
ꢄ
ꢅ
ꢈ
ꢁ
$
%
&
'
(
)
ꢉ
ꢆ
ꢇ
ꢂ
1&
1&
1&
1&
9''
966
9664
9''4
1&
'46
9664
9664
1&
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'46
1&
9''4
9''4
9''4
9''4
*
+
-
'4ꢃ
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9664
9664
1&
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9''/
95()
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9''
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.
/
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%$ꢀ
$ꢃꢀꢌ$3
$ꢅ
:(
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2'7
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&6
9''
0
1
3
5
7
$ꢀ
966
$ꢁ
$ꢉ
$ꢈ
966
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$ꢂ
$ꢃꢃ
1&
$ꢇ
9''
$ꢃꢄ
1&
1&ꢊꢋ$ꢃꢅ
8
9
:
1&
1&
1&
1&
0337ꢀꢁꢂꢀ
Note: VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS and
SSQ are isolated on the device.
V
Rev. 1.3, 2007-07
12
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
