Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 4
Single-ended AC Input Test Conditions Diagram
9''4
9,+ꢎDFꢏPLQ
9,+ꢎGFꢏPLQ
95()
96:,1*ꢎ0$;ꢏ
9,/ꢎGFꢏPD[
9,/ꢎDFꢏPD[
966
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95()ꢋꢐꢋ9,/ꢎDFꢏPD[
'HOWDꢋ7)
9,+ꢎDFꢏPLQꢋꢐꢋ95()
)DOOLQJꢋ6OHZꢋ
5LVLQJꢋ6OHZꢋ
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03(7ꢀꢅꢃꢀ
TABLE 36
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
Max.
Unit
Note
1)
2)
3)
4)
5)
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
DC input signal voltage
–0.3
V
V
V
DDQ + 0.3
—
—
V
DC differential input voltage
AC differential input voltage
AC differential cross point input voltage
0.25
DDQ + 0.6
DDQ + 0.6
0.5
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125
V
1)
2)
3)
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
Rev. 1.3, 2007-07
35
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
